This invention relates to a nonvolatile semiconductor memory and more particularly to an electrically erasable programmable semiconductor memory (EEPROM) which can be used in a NOR type flash memory, for example.
As an EEPROM including memory cells each of which has a gate structure having a floating gate and a control gate stacked thereon to store data "0" or "1" in a nonvolatile fashion by changing the number of electrons stored in the floating gate, a NOR type flash memory is known, for example. The flash memory includes a memory cell array having memory cells arranged in an array form and data stored in the memory cells can be simultaneously erased for the whole memory cell array or for each block unit.
This type of NOR type flash memory is described in IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 27, NO. 11, NOVEMBER 1992 pp. 1540-1545, Umezawa et al. "A 5-V-Only Operation 0.6 .mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure" and IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 27, NO. 11, NOVEMBER 1992 pp. 1547-1553, Jinbo et al. "A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode", for example.
FIGS. 1A to 1C schematically show the structure of the memory cell in the NOR type flash memory. FIG. 1A is a pattern plan view, FIG. 1B is a cross sectional view taken along the 1B--1B line of FIG. 1A and FIG. 1C is a cross sectional view taken along the 1C--1C line of FIG. 1A.
As shown in FIGS. 1A to 1C, an N-type well 1b is formed in a P-type semiconductor substrate 1a and a P-type well 1c for forming a cell area is formed in the N-type well 1b. A cell array is formed on the P-type well 1c. An element isolation insulating film 2 is disposed over the main surface of the substrate 1a to electrically isolate the memory cells. A gate oxide film 3 is formed over the main surface of the substrate 1a (on the P-type well 1c) isolated by the element isolation insulating film 2. A floating gate 4 of each cell is formed on the gate oxide film 3 of the cell. An insulating film (an insulating film between the floating gate and the control gate) 6 is formed on the floating gate 4. A control gate 5 of the cell is formed on the insulating film 6 to cover the floating gates of the adjacent cells. An inter-level insulating film 7 is formed on the resultant semiconductor structure. A bit line 8 is formed on the inter-level insulating film 7 to extend in a direction intersecting the control gate 5. A drain region (n-type diffusion layer) 9 and a source region (n-type diffusion layer, source line) 10 of the cell are separately formed in the P-type well 1c below the stacked gate structure. A through hole 12 is formed in the inter-level insulating film 7 on the drain region 9 to permit the drain region 9 and the bit line 8 to be connected at a bit contact portion 11.
As described above, the memory cell has the drain 9, source 10, floating gate 4 and control gate 5 and stores data by changing the amount of charges stored in the floating gate 4.
FIG. 2 is a circuit diagram showing an example of the construction of a memory cell array having memory cells which are the same in construction as the memory cell shown in FIGS. 1A to 1C arranged in a matrix form.
The gate electrodes of memory cells MC00 to MCn0, MC01 to MCn1, . . . , or MC0m to MCnm on the same row are connected to a corresponding one of word lines WL0 to WLn, the drain electrodes thereof on the same column are connected to a corresponding one of bit lines BL0 to BLm, and the source electrodes thereof are commonly connected to a source line SL.
Among the NOR type flash memory, a memory of plural-bit configuration for simultaneously inputting/outputting data of plural bits with respect to the exterior at the time of data programming/data readout is provided and a memory of 16-bit configuration having the bit width of 16 is known as one example.
In the NOR type flash memory of plural-bit configuration, the same cell array block is divided into N groups in the unit of plural columns. Memory cells of the N groups are selected by use of the same row selection signal at the time of data readout/data programming and one memory cell is selected from the memory cells of each of the N groups by use of a column selection signal so that N memory cells can be simultaneously selected.
FIG. 3 shows an extracted part of the cell array block in the NOR type flash memory of plural-bit configuration and an extracted part of a peripheral circuit associated therewith.
Bit lines are divided into groups BL0 to BL15, . . . each including four bit lines, for example, one-side ends of the current paths of column selection transistors CS are respectively connected to one-side ends of the four bit lines of each of the groups BL0 to BL15, . . . and the other ends of the current paths of the four column selection transistors CS are commonly connected to make a common bit line. The common bit line is connected to one end of a bit line load (bit line load transistor) LT, an input terminal of a sense amplifier SA, one end of the current path of a programming transistor WT and the like via the current path of a bit line potential clamping transistor CT. The other ends of the current paths of the bit line load transistor LT and programming transistor WT are connected to power supplies.
In the NOR type flash memory of plural-bit configuration, each of the bit lines BL0 to BL15 and BL16 to BLm in FIG. 2 corresponds to one of the four bit lines of each of the groups BL0 to BL15, . . .
When data re-programming is effected for a memory cell in the NOR type flash memory, in order to prevent occurrence of a phenomenon (disturb at the time of re-programming of data) that another memory cell commonly using the bit line or word line with the memory cell for data re-programming is set into a half-selected state and the data storing state thereof is changed, the word line/bit line is separated for each block unit to be erased. The block unit to be erased is generally 512 kbits and, for example, a cell block array of 1 k word lines.times.512 bit lines configuration or 512 word lines.times.1 kbit lines configuration is used.
Next, the data programming, readout and erasing operations in the NOR type flash memory with the above construction are explained.
(1) When the memory cells MC00 to MC015 are selected at the time of data programming, a voltage of Vpp (a voltage of approx. 10V) is applied to the selected word line WL0 commonly used by the memory cells MC00 to MC015 and the other non-selected word lines WL1 to WLn are set to 0V.
Bit line voltages applied to the selected bit lines BL0 to BL15 respectively connected to the selected memory cells MC00 to MC015 depend on programming data, and Vdp (a voltage of approx. 5V) is applied to the bit line corresponding to data "0" to be programmed and 0V is applied to the bit line corresponding to data "1" to be programmed. The source line SL is set at 0V.
Thus, in the selected memory cell into which data "0" is programmed among the selected memory cells MC00 to MC015, the gate is set at Vpp and the drain is set at Vdp. Among the electrons moving from the source to the drain, some electrons have a large amount of energy so as to reach the floating gate by the electric field in the gate direction. Then, the "1" data state in which the number of electrons in the floating gate is relatively small is changed into the "0" data state in which the number of electrons in the floating gate is relatively large.
In the memory cells having the gate voltage-drain voltage relation different from the above relation (in the non-selected memory cell and the selected memory cell into which "1" data is programmed), no drain current flows and data in the memory cell is not changed.
(2) When the memory cells MC00 to MC015 are selected at the time of data readout, Vcc (a voltage of approx. 5V) is applied to the selected word line WL0 commonly used by the above memory cells and the other non-selected word lines WL1 to WLn are set to 0V.
Bit line voltages applied to the selected bit lines BL0 to BL15 respectively connected to the selected memory cells MC00 to MC015 are set to Vd (a voltage of approx. 1V) by use of the bit line clamping transistor and 0V is applied to the non-selected bit lines. The source line SL is set at 0V.
At this time, since the threshold voltage of the memory cell in the "1" data state among the selected memory cells MC00 to MC015 is lower than Vcc and the threshold voltage of the memory cell in the "0" data state is higher than Vcc, a current flows in the "1" cell and no current flows in the "0" cell. "0" data or "1" data can be read out by sensing a voltage corresponding to the above current by use of the sense amplifier.
(3) The erase operation is simultaneously effected for a selected array block at the time of data erasing (one type of data programming). In this case, a method for applying an erase voltage to the source line SL of the block to be erased and a method for applying an erase voltage to the cell well of the block to be erased are provided.
The former erase method is effected by setting all of the word lines in the block to be erased to 0V or less and applying a high erase voltage to the source line SL. Thus, a high electric field is applied to the gate oxide film of an overlapping portion between the source region and the floating gate in all of the memory cells in the block to be erased and electrons in the floating gate pass into the source region by tunneling so that data in all of the memory cells will become "1".
In the non-selected cell array block, all of the word lines are set at 0V and the source line SL is set at 0V, and therefore, data of the memory cells will not disappear.
The latter erase method is effected by setting all of the word lines in the block to be erased to 0V and applying a high erase voltage to the P-type well and N-type well. Thus, a high electric field is applied to the gate oxide film between the well and the floating gate in all of the memory cells in the block to be erased and electrons in the floating gate pass into the well so that data in all of the memory cells will become "1".
In the non-selected cell array block, all of the word lines are set at 0V and the wells are set at 0V, and therefore, data of the memory cell will not disappear.
In order to form the power supply of the flash memory which requires an erase voltage and a programming voltage higher than the power supply voltage (approx. 5V) as a single power supply and realize the flash memory with the single power supply, a booster circuit for raising the programming voltage and a booster circuit for raising the erase voltage are provided in the chip.
The pattern areas required for causing the booster circuits to have necessary current supply abilities and the currents consumed in the operations thereof depend on the ratio of the programming/erase voltage and the power supply voltage.
It is required to lower the operation voltage of the flash memory, but if the programming/erase voltage cannot be lowered, the pattern area required for the booster circuit increases, and as a result, the current consumed increases. Therefore, in the conventional NOR type flash memory, the area of the programming voltage booster circuit and the consumption current are increased. The reason is described below.
FIG. 4 shows a characteristic of a change in the threshold voltage with the programming time in each memory cell MCi and FIG. 5 shows a characteristic of a change in the programming current (drain current) with the programming time.
As is clearly understood from the characteristic diagrams of FIGS. 4 and 5, the threshold voltage of the memory cell is low at the initial time of programming, and therefore, the drain current becomes large (the initial value thereof is 450 .mu.A).
The conventional programming method is to simultaneously program programming bits of a bit width into a plurality of memory cells of the same cell array block and since a large programming current flows particularly when "0" data is programmed into all of the selected memory cells, the area required for the programming voltage booster circuit to fully supply the above current and the consumption current are increased.
As a method for reducing the area of the programming voltage booster circuit and the consumption current, for example, a method for reducing the area of the programming voltage booster circuit and the consumption current by half by dividing the programming bits into two portions and simply time-dividing the programming operation like the programming signals shown in FIG. 6 is proposed. For example, this technique is described in 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 172-173, June 1996, J C Chen et al. "A 2.7V only 8 Mb.times.16 NOR Flash Memory.
That is, the method is to reduce the number of bits to be simultaneously programmed to half (8) of the bit width so as to reduce the current supply ability required for the programming voltage booster circuit by half in the NOR type flash memory of the bit width 16. However, if the technique is used, the programming time is doubled.
In the conventional NOR type flash memory, the area of the erase voltage booster circuit and the consumption current are increased and the reason is described below.
FIG. 7 shows a characteristic of a change in the threshold voltage with the erase time in each memory cell MCi and FIG. 8 shows a characteristic of a change in the erase current (source current) with the erase time.
As is clearly understood from the characteristic diagrams of FIGS. 7 and 8, the threshold voltage of the memory cell is high and an electric field in the tunnel oxide film is high at the initial time of erasing and the band-band tunnel current is large (4 mA at maximum).
Further, in order to sufficiently supply the band-band tunnel current, the size of the erase voltage booster circuit is so determined as to set the supply current of the erase voltage booster circuit to the maximum value of 4 mA corresponding to the initial value of the band-band tunnel current. Therefore, the area required for the erase voltage booster circuit and the consumption current are increased.
In this case, since the erase size is determined to 512 kbits by the specification, the necessary supply current in the conventional simultaneous erase method cannot be reduced.
In the conventional NOR type flash memory, if a plurality of memory cells in the same cell array block are simultaneously selected at the time of data programming and data is simultaneously programmed, the drain currents (programming currents) of the cells to be simultaneously programmed are concentrated on the source line SL common for the cells, and therefore, if the number of bits to be simultaneously programmed is increased, the source line potential rises by the parasitic resistance of the common source line SL and the maximum number of bits which can be simultaneously programmed is determined by the programmable critical source voltage Vc, and thus, a problem that the number of bits to be simultaneously programmed is limited occurs. The problem is described below.
FIG. 9 schematically shows one example of part of a cell array block in the conventional NOR type flash memory and column gates (column selection transistors and block selection transistors).
The cell array block includes a plurality of memory cells MC arranged in a matrix form (in this example, cells of only one row are extracted and shown as a representative for brevity of the drawing). A word line WLi is commonly connected to the control gates of the memory cells of the same row and a bit line BLi is commonly connected to one-side ends of the memory cells of the same column. In other words, desired two memory cells of the same row or the same column commonly use the word line or bit line.
Each bit line is serially connected to the current paths of the column selection transistor and the block selection transistor and a data line DL is commonly connected to one-side ends of the current paths of the block selection transistors for every preset number of bit lines.
In the above NOR type flash memory, one or a plurality of memory cells of the cell array block are simultaneously selected at the time of data readout, programming or erase.
The memory cells to be simultaneously programmed are present in the same cell array block and the column selection signal and block selection signal for the selected column are set to the "H" level.
In this case, the drain currents (programming currents) of the cells to be simultaneously programmed are concentrated on the common source line SL at the time of data programming, and therefore, if the number of bits to be simultaneously programmed in the same cell array block is increased, the source line potential rises by the parasitic resistance Rs of the common source line SL and the maximum number of bits which can be simultaneously programmed is determined by the programmable critical source voltage Vc. Thus, the number of bits to be simultaneously programmed is limited.
That is, if the number of bits to be simultaneously programmed is excessively large, the source potential of the memory cell rises and the drain current becomes difficult to flow, and as a result, the programming characteristic is deteriorated.
Further, holes generated in the programming operation become difficult to flow by the resistance of the P-type well in which the memory cells are formed and the potential of the P-type well rises to cause the punch-through phenomenon.
Therefore, in the case of programming test, the erase time for each bit is short since the erase operation is simultaneously effected for the cell array block, but the programming time for each bit becomes long because of the restriction on the number of bits which can be simultaneously programmed and an increase in the test time causes the test cost to rise.
As described above, in the conventional nonvolatile semiconductor memory, since a large programming current flows particularly when "0" data is programmed into all of the selected memory cells in a case where programming bits of the bit width are simultaneously programmed into a plurality of memory cells of the same cell array block, a problem that the area required for the programming voltage booster circuit to sufficiently supply the above current and the consumption current are increased occurs.
Further, in the conventional simultaneous erase method and there occurs a problem that a necessary supply current becomes large and the area required for the programming voltage booster circuit and the consumption current are increased.
The test time becomes long because of the restriction on the number of bits which can be simultaneously programmed, and as a result, a problem that the test cost rises occurs.